我来翻吧。一句一句翻，大家看我翻的对不对。
===============================
Preliminary Information: SteadyClock™
RME's latest Clock technology - Theory and Operation
初步认识：SteadyClock（注册商标）
RME 的最新时钟技术
The SteadyClock technology of RME's latest products guarantees an excellent performance in all clock modes. Its highly efficient jitter suppression enables ADI-648, HDSP 9632 and HDSP MADI to refresh and clean up any clock signal, and to provide the clock signal as reference clock at the word clock output.
RME 最新产品中的 SteadyClock 技术保证了在所有时钟模式下的极好的性能。它具有非常有效的 jitter 抑制能力，能让 ADI-648、HDSP 9632 和 HDSP MADI（这几个都是具备了 SteadyClock 技术的产品）把任何时钟信号都“清洗干净”，并且提供了等同于字时钟输出的时钟信号。
Theory
理论讲解
Usually a clock section consists of an analog PLL for external synchronization and several quartz oscillators for internal synchronisation. SteadyClock requires only one quartz, using a frequency not equalling digital audio. Latest circuit designs like hi-speed digital synthesizer, a fully digital PLL, 200 MHz sample rate and analog filtering allow RME to realize a completely newly developed clock technologie, right within the FPGA at lowest costs. The clock's performance exceeds even professional expectations. Despite its remarkable features, SteadyClock reacts quite fast compared to other techniques. It locks in fractions of a second to the input signal, follows even extreme varipitch changes with phase accuracy, and locks directly within a range of 25 kHz up to 200 kHz.
通常，电路中的时钟部份包括一个用于外部同步的模拟的 PLL 和几个用于内部同步的石英振荡器。SteadyClock 技术仅仅需要一个石英，使用一个与数字音频不相等的频率。最近的电路设计，象高速数字合成器、完全的数字 PLL、200 MHz 采样率和模拟滤波，允许 RME 实现一个完全新型的增强的时钟技术，封装在 FPGA 里，成本很低。这个时钟的性能甚至超过了专业期望值。除了它非凡的功能外，SteadyClock 还………………（看不懂了）
Measurements
测量
SteadyClock has originally been developed to gain a stable and clean clock from the heavily jittery MADI data signal. The embedded MADI clock suffers from about 80 ns jitter, caused by the time resolution of 125 MHz within the format. Common jitter values for other devices are 5 ns, while a very good clock will have less than 2 ns.
SteadyClock 最初是为了增强 MADI 数字信号中那带有严重的 jitter 问题的时钟的稳定和清洁而开发的。（注：MADI 是一种数字信号格式，类似于 ADAT ，也是多通道的，用一根光纤线或同轴线来传输，一根线可以传 64 通道音频） 一般的 MADI 时钟有大约 80 ns 的 jitter ，由格式中的 125 MHz 时间决议引发。而其他数字传输格式通常只有 5 ns 的 jitter ，好的时钟的 jitter 小于 2 ns 。
The picture to the right shows the MADI input signal with 80 ns of jitter (top graph, yellow). Thanks to SteadyClock this signal turns into a clock with less than 2 ns jitter (lower graph, blue).
下面这张图显示了带有 80 ns 的 jitter 的 MADI 输入信号（黄色线条）。而使用 SteadyClock 技术后，jitter 减小到低于 2 ns（蓝色线条）。
![]()
Using other input sources like AES, SPDIF, word clock or ADAT, one most probably never experiences such high jitter values. But SteadyClock is not only ready for them, it would handle them just on the fly.
使用其他输入源诸如 AES, SPDIF, 字时钟，ADAT 时，一般不会有这么大的 jitter 。但是 SteadyClock 也能解决它们的问题。
The screnshot to the right shows an extremely jittery word clock signal of about 50 ns jitter (top graph, yellow). Again SteadyClock provides an extreme clean-up. The filtered clock shows less than 2 ns jitter (lower graph, blue).
下图中显示出了一个具有非常大的 jitter 的字时钟信号，大约有 50 ns（黄色线条）。SteadyClock 又一次把它减小到了低于 2 ns（蓝色线条）。
![]()
Real-world Operation
真实操作
The following example shows SteadyClock's behaviour in real-world operation. The ADAT input of the HDSP 9632 uses an advanced Bitclock PLL. But this PLL does not provide any jitter suppression within the audio range. Therefore the quality of the clock extracted from the ADAT signal depends on the specific ADAT source.
下一个例子显示了 SteadyClock 在实际操作中的作用。HDSP 9632 的 ADAT 输入使用一个增强的 Bitclock PLL（一种极好的光纤信号接收电路，本身的 jitter 非常小）。但是这个 PLL 在音频范畴内不能抑制任何 jitter 。因此这个 ADAT 信号的时钟质量就取决于外部的 ADAT 信号源。
But on the HDSP 9632 (also ADI-648 and HDSP MADI), SteadyClock will process the ADAT clock signal after its extraction.
但是 HDSP 9632 具有 SteadyClock 技术，SteadyClock 将会把 ADAT 时钟信号进行处理（净化）。
The picture to the right shows the word clock output of the HDSP 9632, which is directly fed from the internal master clock - and with this from SteadyClock.
下图显示了 HDSP 9632 的字时钟输出，它是直接被内部主时钟驱动的，也使用了 SteadyClock 技术。
![]()
In this case the card is set to AutoSync, and receives an ADAT signal with very low jitter (below 1 ns). The remaining jitter behind BitClock PLL and SteadyClock is hard to detect at all, with a value of around 700 ps (0.7 ns).
在这个例子里声卡被设置成了 AutoSync（一种自动同步技术，如果声卡连接了外部设备的话，声卡会自动把时钟切换成外部时钟），声卡接收到了一个具有极低 jitter（小于 1 ns）的 ADAT 信号。SteadyClock 很难发现这个 jitter ，所以这个 jitter 仍然被保留，大约是 700 ps（0.7 ns）。
This picture shows the same situation with an ADAT signal of about 40 ns of jitter. The input jitter is nearly completely removed, the output of the HDSP 9632 again shows around 700 ps (0.7 ns).
下图中显示的是同样的状态，只是外部的 ADAT 信号的 jitter 增大到了 40 ns 。而这个输入的 jitter 却被几乎全部消灭了（被 SteadyClock 技术），HDSP 9632 的输出又一次是 700 ps（0.7 ns）。
![]()
The signal processed by SteadyClock is used internally to clock on-board AD- and DA-converters, and to clock the digital outputs. Additionally it is available directly at the word clock outputs.
在这个例子里，被 SteadyClock 处理之后的信号被用来给声卡上的 AD 和 DA 作为时钟使用，也给数字输出作时钟，另外它也能直接给字时钟输出使用。
Conclusion
总结
The cleaned and jitter-freed clock signal can be used as reference clock in any application. And the quality of the external (input) clock doesn't matter anymore.
被清洁 jitter 之后的时钟信号可以用来给任何东西用作参考时钟。外部（输入）时钟的质量无关紧要，随便！
===============================
Preliminary Information: SteadyClock™
RME's latest Clock technology - Theory and Operation
初步认识：SteadyClock（注册商标）
RME 的最新时钟技术
The SteadyClock technology of RME's latest products guarantees an excellent performance in all clock modes. Its highly efficient jitter suppression enables ADI-648, HDSP 9632 and HDSP MADI to refresh and clean up any clock signal, and to provide the clock signal as reference clock at the word clock output.
RME 最新产品中的 SteadyClock 技术保证了在所有时钟模式下的极好的性能。它具有非常有效的 jitter 抑制能力，能让 ADI-648、HDSP 9632 和 HDSP MADI（这几个都是具备了 SteadyClock 技术的产品）把任何时钟信号都“清洗干净”，并且提供了等同于字时钟输出的时钟信号。
Theory
理论讲解
Usually a clock section consists of an analog PLL for external synchronization and several quartz oscillators for internal synchronisation. SteadyClock requires only one quartz, using a frequency not equalling digital audio. Latest circuit designs like hi-speed digital synthesizer, a fully digital PLL, 200 MHz sample rate and analog filtering allow RME to realize a completely newly developed clock technologie, right within the FPGA at lowest costs. The clock's performance exceeds even professional expectations. Despite its remarkable features, SteadyClock reacts quite fast compared to other techniques. It locks in fractions of a second to the input signal, follows even extreme varipitch changes with phase accuracy, and locks directly within a range of 25 kHz up to 200 kHz.
通常，电路中的时钟部份包括一个用于外部同步的模拟的 PLL 和几个用于内部同步的石英振荡器。SteadyClock 技术仅仅需要一个石英，使用一个与数字音频不相等的频率。最近的电路设计，象高速数字合成器、完全的数字 PLL、200 MHz 采样率和模拟滤波，允许 RME 实现一个完全新型的增强的时钟技术，封装在 FPGA 里，成本很低。这个时钟的性能甚至超过了专业期望值。除了它非凡的功能外，SteadyClock 还………………（看不懂了）
Measurements
测量
SteadyClock has originally been developed to gain a stable and clean clock from the heavily jittery MADI data signal. The embedded MADI clock suffers from about 80 ns jitter, caused by the time resolution of 125 MHz within the format. Common jitter values for other devices are 5 ns, while a very good clock will have less than 2 ns.
SteadyClock 最初是为了增强 MADI 数字信号中那带有严重的 jitter 问题的时钟的稳定和清洁而开发的。（注：MADI 是一种数字信号格式，类似于 ADAT ，也是多通道的，用一根光纤线或同轴线来传输，一根线可以传 64 通道音频） 一般的 MADI 时钟有大约 80 ns 的 jitter ，由格式中的 125 MHz 时间决议引发。而其他数字传输格式通常只有 5 ns 的 jitter ，好的时钟的 jitter 小于 2 ns 。
The picture to the right shows the MADI input signal with 80 ns of jitter (top graph, yellow). Thanks to SteadyClock this signal turns into a clock with less than 2 ns jitter (lower graph, blue).
下面这张图显示了带有 80 ns 的 jitter 的 MADI 输入信号（黄色线条）。而使用 SteadyClock 技术后，jitter 减小到低于 2 ns（蓝色线条）。
Using other input sources like AES, SPDIF, word clock or ADAT, one most probably never experiences such high jitter values. But SteadyClock is not only ready for them, it would handle them just on the fly.
使用其他输入源诸如 AES, SPDIF, 字时钟，ADAT 时，一般不会有这么大的 jitter 。但是 SteadyClock 也能解决它们的问题。
The screnshot to the right shows an extremely jittery word clock signal of about 50 ns jitter (top graph, yellow). Again SteadyClock provides an extreme clean-up. The filtered clock shows less than 2 ns jitter (lower graph, blue).
下图中显示出了一个具有非常大的 jitter 的字时钟信号，大约有 50 ns（黄色线条）。SteadyClock 又一次把它减小到了低于 2 ns（蓝色线条）。
Real-world Operation
真实操作
The following example shows SteadyClock's behaviour in real-world operation. The ADAT input of the HDSP 9632 uses an advanced Bitclock PLL. But this PLL does not provide any jitter suppression within the audio range. Therefore the quality of the clock extracted from the ADAT signal depends on the specific ADAT source.
下一个例子显示了 SteadyClock 在实际操作中的作用。HDSP 9632 的 ADAT 输入使用一个增强的 Bitclock PLL（一种极好的光纤信号接收电路，本身的 jitter 非常小）。但是这个 PLL 在音频范畴内不能抑制任何 jitter 。因此这个 ADAT 信号的时钟质量就取决于外部的 ADAT 信号源。
But on the HDSP 9632 (also ADI-648 and HDSP MADI), SteadyClock will process the ADAT clock signal after its extraction.
但是 HDSP 9632 具有 SteadyClock 技术，SteadyClock 将会把 ADAT 时钟信号进行处理（净化）。
The picture to the right shows the word clock output of the HDSP 9632, which is directly fed from the internal master clock - and with this from SteadyClock.
下图显示了 HDSP 9632 的字时钟输出，它是直接被内部主时钟驱动的，也使用了 SteadyClock 技术。
In this case the card is set to AutoSync, and receives an ADAT signal with very low jitter (below 1 ns). The remaining jitter behind BitClock PLL and SteadyClock is hard to detect at all, with a value of around 700 ps (0.7 ns).
在这个例子里声卡被设置成了 AutoSync（一种自动同步技术，如果声卡连接了外部设备的话，声卡会自动把时钟切换成外部时钟），声卡接收到了一个具有极低 jitter（小于 1 ns）的 ADAT 信号。SteadyClock 很难发现这个 jitter ，所以这个 jitter 仍然被保留，大约是 700 ps（0.7 ns）。
This picture shows the same situation with an ADAT signal of about 40 ns of jitter. The input jitter is nearly completely removed, the output of the HDSP 9632 again shows around 700 ps (0.7 ns).
下图中显示的是同样的状态，只是外部的 ADAT 信号的 jitter 增大到了 40 ns 。而这个输入的 jitter 却被几乎全部消灭了（被 SteadyClock 技术），HDSP 9632 的输出又一次是 700 ps（0.7 ns）。
The signal processed by SteadyClock is used internally to clock on-board AD- and DA-converters, and to clock the digital outputs. Additionally it is available directly at the word clock outputs.
在这个例子里，被 SteadyClock 处理之后的信号被用来给声卡上的 AD 和 DA 作为时钟使用，也给数字输出作时钟，另外它也能直接给字时钟输出使用。
Conclusion
总结
The cleaned and jitter-freed clock signal can be used as reference clock in any application. And the quality of the external (input) clock doesn't matter anymore.
被清洁 jitter 之后的时钟信号可以用来给任何东西用作参考时钟。外部（输入）时钟的质量无关紧要，随便！