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martjay 发表于 23-3-7 14:18
你看看是什么提示
我把下载的DSP56300Emu，Osirus，OsirusFX。3个的vst，vst3文件放在了cubase相应的文件夹里，cubase扫描到了，但是被打入插件黑名单，f11里面没有啊
djsaqir 发表于 23-3-7 15:15
au的直接放au下就能用 vst的mac 没用了可能哪里设置不对 本帖最后由 djsaqir 于 23-3-7 15:50 编辑
我也是，放弃
xiaobaitu 发表于 23-3-6 23:12
我把下载的DSP56300Emu，Osirus，OsirusFX。3个的vst，vst3文件放在了cubase相应的文件夹里，cubase扫描 ...
你需要放Virus C的ROM在同一个文件夹里，你可以把Virus TI2的ROM理解成Virus C的音色预制，
那个.BIN就是Virus C的ROM，需要有核心才能运行起来，你必须有系统核心，才能运行预制。
Osirus那两个VST2我改名成了Virus C，去看DSP那个帖子吧。
本帖最后由 martjay 于 23-3-7 03:09 编辑
zs 发表于 23-3-7 04:31
Osirus和OsirusFX，还有Osirus clap这几个有啥用？
不放入它们，只有DSP56300Emu.dll和bin就可以用啊。
对，fx比如一些用来做vocal效果器的时候用，比如daft punk，ti2就把它当预制就好了
martjay 发表于 23-3-7 13:19
他的博客放视频了Q已经出声了
复刻自己用还行拿来卖就要打官司了，但是你会搞硬件吗？
我们得到的 512k Access Virus 固件ROM 就是这块 Flash 闪存颗粒里面的内容
Am29F040 20 年前的科技产物。
我也只能买一块 Am29F040 把固件烧写进去，DSP53xx货源好像还有库存
然后呢，然后就没有然后了
其他 Access Virus PCB 资料一点都查不到，瞎费功夫了。
Am29F040
512K × 24-bit Shared Memory Flash Example
This example implements a 512K × 24-bit word memory space that is accessible as program, X data, and Y data memory. This design uses three AMD Am29F040 devices. See Figure 3 for the memory map layout, Figure 4 for the block diagram, Example 1 for the program, and Figure 5 for the schematic. Since the program, X data and Y data spaces are shared, any location referenced by a program memory access also accesses the same memory location during an X data or Y data access. Since the Flash memory is in the DSP program space, program control can be turned over to the program in Flash at $C00000 at reset. This allows an embedded application to boot and run directly from Flash, using the internal 1 K program cache to help speed repeated program operations. Since the X data and Y data spaces also access the Flash, data can be stored in the Flash for use after boot.
For this example, the DSP core runs at 80 MHz, generated by the PLL from a 4.000 MHz crystal. The memory bank consists of three AMD Am29F040 devices, which are organized as 512K × 8-bits to provide a 24-bit word.
These are 5 V devices, with a 90 nS access time. The 90 S access time requires eight wait states for correct operation.
The DSP56303 data bus is not 5 V tolerant, so level converters are needed to interface with the 5 V memory devices. The devices used are Quality Semiconductor QS3245 QuickSwitch® 8-bit Bus Switches. These switches allow the connection of 3.3 V CMOS logic (the DSP data bus) on one side and 5 V TTL-compatible logic (the memory devices) on the other side, effectively providing a 3.3 V to 5 V level conversion. The propagation delay of the switch is 0.25 nS, which is not significant in this design.
This example demonstrates a minimal external memory design using a single bank of Flash memory in the external memory spaces. If you add more memory or other devices to the bus, additional address decode logic may be needed.
After reset with Mode 0 selected, the DSP starts fetching instructions from external memory at location
P: $C00000. Although this DSP core uses 24-bit addressing internally, only eighteen external address lines (A0-A17) are provided. Consequently, the top six bits are stripped, and the address presented on the address bus is $000000. The Flash memory is configured to respond to all external memory requests, as CE is asserted at all times. Since the eighteen bits can address only 256K words, only the first 256K words of the Flash are accessible, and data aliasing occurs every 256K words (i.e., accessing location 256K returns the contents of the same Flash
This example implements a 512K × 24-bit word memory space that is accessible as program, X data, and Y data memory. This design uses three AMD Am29F040 devices. See Figure 3 for the memory map layout, Figure 4 for the block diagram, Example 1 for the program, and Figure 5 for the schematic. Since the program, X data and Y data spaces are shared, any location referenced by a program memory access also accesses the same memory location during an X data or Y data access. Since the Flash memory is in the DSP program space, program control can be turned over to the program in Flash at $C00000 at reset. This allows an embedded application to boot and run directly from Flash, using the internal 1 K program cache to help speed repeated program operations. Since the X data and Y data spaces also access the Flash, data can be stored in the Flash for use after boot.
For this example, the DSP core runs at 80 MHz, generated by the PLL from a 4.000 MHz crystal. The memory bank consists of three AMD Am29F040 devices, which are organized as 512K × 8-bits to provide a 24-bit word.
These are 5 V devices, with a 90 nS access time. The 90 S access time requires eight wait states for correct operation.
The DSP56303 data bus is not 5 V tolerant, so level converters are needed to interface with the 5 V memory devices. The devices used are Quality Semiconductor QS3245 QuickSwitch® 8-bit Bus Switches. These switches allow the connection of 3.3 V CMOS logic (the DSP data bus) on one side and 5 V TTL-compatible logic (the memory devices) on the other side, effectively providing a 3.3 V to 5 V level conversion. The propagation delay of the switch is 0.25 nS, which is not significant in this design.
This example demonstrates a minimal external memory design using a single bank of Flash memory in the external memory spaces. If you add more memory or other devices to the bus, additional address decode logic may be needed.
After reset with Mode 0 selected, the DSP starts fetching instructions from external memory at location
P: $C00000. Although this DSP core uses 24-bit addressing internally, only eighteen external address lines (A0-A17) are provided. Consequently, the top six bits are stripped, and the address presented on the address bus is $000000. The Flash memory is configured to respond to all external memory requests, as CE is asserted at all times. Since the eighteen bits can address only 256K words, only the first 256K words of the Flash are accessible, and data aliasing occurs every 256K words (i.e., accessing location 256K returns the contents of the same Flash